A FPGA Configuration Method for Improving System Initial Efficiency

doi:10.3969/j.issn.1006-2475.2012.07.060

Computer and Modernization ›› 2012, Vol. 203 ›› Issue (7): 215-217.doi: 10.3969/j.issn.1006-2475.2012.07.060

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A FPGA Configuration Method for Improving System Initial Efficiency

XIE Ting-ting

Department of Computer and Information Science， Fujian University of Technology， Fuzhou 350108， China

Received:2012-03-07 Revised:1900-01-01 Online:2012-08-10 Published:2012-08-10

Abstract

Abstract: This paper presents a FPGA configuration method composed by master controller CPU, CPLD and RAM Flash. RAM Flash is used to store FPGA configuration data, and CPLD reads the configuration data from RAM flash. FPP (Fast Passive Parallel) method is adopted to configure FPGA. The main controller communicates with CPLD through its interfaces to update and maintain configuration data of RAM Flash. This paper also introduces several applications for this method.

Key words: configuration method, CPLD, FPGA

CLC Number:

TP368.1

XIE Ting-ting. A FPGA Configuration Method for Improving System Initial Efficiency[J]. Computer and Modernization, 2012, 203(7): 215-217.

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A FPGA Configuration Method for Improving System Initial Efficiency

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